Field of the Invention
The invention relates to a decoder circuit for driving a selected instance from a set of N output lines on the basis of an M-bit address and in response to a turn-on signal. The decoder circuit of this type includes: a number Kxe2x89xa72 of parallel input decoders, each of which receives an associated segment of the M-bit address and, for each bit pattern to be expected for this segment, activates precisely one instance of its outputs which is uniquely associated with this bit pattern; an output decoder which contains, for each of the N output lines, a separate drive path having a plurality of controllable switches whose switching paths are arranged in series between the output line in question and a drive potential; a coupling network for coupling each of the N different subsets of the input decoder outputs, which respectively contain one output of each of the K input decoders, to the control connections of K instances of the controllable switches in one instance of the N drive paths which is associated with the subset in question, such that these switches turn on when those instances of the input decoder outputs which are coupled to them have been activated.
The drive paths are connected through only during the appearance of a turn-on signal.
Such 1-out-of-N decoders are known in general and they are conventionally used to address row and column selection lines on a matrix of memory cells. This is also the preferred field of application of the present invention.
If the number N of output lines to be selectively driven is relatively high, such as in the case of addressing in a memory matrix, the 1-out-of-N decoding is usually performed in sub steps. In this context, the M-bit address is split into K segments, where the number mk of bits in the individual segments may be the same or different. For the K address segments, a group of K parallel 1-out-of-mk input decoders is used, each of which receives the bits of a segment associated with it and, for each bit pattern to be expected for this segment, activates precisely one instance of its mk outputs which is associated with this bit pattern. Hence, in the full set of all the input decoder outputs, only a subset is ever activated, which comprises precisely K outputs, a respective one from each input decoder. In total, there are N such subsets, corresponding to the N possible bit combinations which can be expected in the M-bit address for addressing the N output lines. The M-bit address received on the input decoders thus determines which of the subsets of input decoder outputs is activated.
For further decoding of the address and for driving the respectively addressed output line, each of the N subsets of the input decoder outputs mentioned is connected to K control inputs of an individually associated combinational logic circuit in an output decoder. Accordingly, the output decoder contains N such combinational logic circuits, a respective one for each of the N output lines. In known address decoders, as are customary in connection with memory matrices, for example, each of these combinational logic circuits comprises a drive path containing K+1 switches in series. This drive path is arranged between the output line in question and a potential source supplying the electric xe2x80x9cdrive potentialxe2x80x9d to which the output lines are to be connected in the driven state. The control connections of K instances of these switches in each drive path form the control inputs connected to the K associated input decoder outputs. Each of these K switches is connected (i.e. on) only when the input decoder output connected to its control connection has been activated. The control connection of the (K+1)th switch is connected for receiving the turn-on signal; this switch is on only during the active state of the turn-on signal.
In some applications of a multistage 1-out-of-N decoder system containing K input decoders and an output decoder, only limited space is available for each of the N drive paths in the output decoder. This is true particularly if the system is used as an address decoder for selecting word lines or word line groups or else bit lines in a memory matrix and is integrated on the same chip as the matrix. In this case, for layout reasons, it is usually imperative for the individual drive paths of the output decoder, e.g. for the word lines, to be arranged such that their longitudinal extent firstly runs transversely with respect to the direction of the word lines and secondly does not exceed a particular measure. This measure depends on the distance between the individual word lines and on how many word lines are associated with each of the N output lines or with each of the drive paths of the output decoder. The closer the word lines are arranged next to one another, the less space is ultimately available for the longitudinal extent of a drive path. This space has to accommodate the series of switches contained in the drive path.
This space requirement creates problems, particularly when, as is usual, the K+1 switches in each drive path are in the form of field effect transistors (FETs), in particular MOS-type transistors (MOSFETs), whose channels form the switching paths and whose gates form the control electrodes. For a field effect transistor to turn off reliably, the channel between the source and the drain needs to have a certain minimum length. This sets a lower limit for the total length of the drive path and hence a lower limit for the distance between the word lines. This, of course, conflicts with the desire for increasing miniaturization of memory chips.
It is therefore desirable to optimize the field effect transistors used in this context such that the ratio of their channel length to their total dimension is as high as possible. It is known that, during photolithographic fabrication of field effect transistors, there is a tendency for the charge carriers implanted in the source and drain zones after they have been formed to diffuse into the adjacent region of the channel zone during subsequent high-temperature processing steps, and hence to reduce the effective length of the channel. This disadvantageous effect can be eliminated by following application of the gate oxide with implantation of charge carriers of opposite conduction type into the border regions between the channel on the one hand and the source and drain on the other. Since these boundary regions are covered by the gate oxide, they can only be hit if implantation is carried out from a very oblique direction under the lateral edge of the gate oxide. This measure is known as xe2x80x9chalo implantationxe2x80x9d and is also customary when fabricating switching transistors for the drive paths in the output decoder of word line addressing circuits.
On an integrated series circuit having a plurality of field effect transistors, optimizing halo implantation can be performed effectively only if the transistors are at a certain minimum distance from one another. This is because, with a very close arrangement, the gaps between the gate oxide regions of adjacent transistors are too narrow to allow unimpeded oblique irradiation of the implant material under the lateral edges of the gate oxide. The desired and inherently advantageous halo implantation thus sets a new limit for miniaturization.
The problems described above are just a few of the more prevalent and important examples of the drawbacks of the prior art multistage 1-out-of-N decoder circuits.
It is accordingly an object of the invention to provide a decoder circuit, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which is designed such that the space required for the drive paths in the output decoder can be used more advantageously than previously. It is a particular object of the invention to allow the interspace between the switches in each drive path to be made larger than previously without needing to increase the size of the space for the total length of the drive path.
With the foregoing and other objects in view there is provided, in accordance with the invention, a decoder circuit for driving a selected instance of a set of N output lines on the basis of an M-bit address and in response to a turn-on signal, the decoder circuit comprising:
a number Kxe2x89xa72 of parallel input decoders having a plurality of inputs together receiving an M-bit address, a plurality of input decoder outputs, and each receiving a respectively associated segment of the M-bit address and, for each bit pattern to be expected for the segment, activating precisely one instance of the outputs uniquely associated with the bit pattern;
an output decoder having, for each of the N output lines, a separate drive path with a plurality of controllable switches having switching paths in series between the respective output line and a drive potential;
a coupling network for coupling each of N different subsets of the input decoder outputs, which respectively contain one output of each of the K input decoders, to the control connections of K instances of the controllable switches in one instance of the N drive paths associated with the subset in question, such that the switches turn on when those instances of the input decoder outputs coupled thereto have been activated; and
a combinational logic device connected to all the outputs of one of the input decoders and having an input receiving a turn-on signal and configured to permit the drive paths to be connected through only when the turn-on signal appears, whereby the combinational logic device responds to the turn-on signal by enabling the outputs to be coupled to the control connections of the switches associated with the outputs in the drive paths only during the appearance of the turn-on signal.
In accordance with an added feature of the invention, the decoder circuit is commonly integrated with a memory matrix on a semiconductor chip and forms an address decoder for addressing N subsets of a plurality of mutually parallel selection lines in the memory matrix. Each of the output lines is connected to the connection device for an associated subset of the selection lines, and a series circuit comprising the switches is arranged, along a length thereof, in each drive path transversely with respect to the selection lines in the memory matrix.
In accordance with an additional feature of the invention, the switches in each drive path are field effect transistors having channels forming the switching paths and gate electrodes forming the control connections.
In accordance with another feature of the invention, the field effect transistors forming the switches in the drive paths are optimized by halo implants at respective ends of the channels thereof.
In accordance with a concomitant feature of the invention, each of the output lines is connected to the connection device for an associated subset of the word lines in the memory matrix.
In other words, a decoder circuit for driving a selected instance from a set of N output lines on the basis of an M-bit address and in response to a turn-on signal has a number Kxe2x89xa72 of parallel input decoders, each of which receives an associated segment of the M-bit address and, for each bit pattern to be expected for this segment, activates precisely one instance of its outputs which is uniquely associated with this bit pattern. An output decoder contains, for each of the N output lines, a separate drive path having a plurality of controllable switches whose switching paths are arranged in series between the output line in question and a drive potential. A coupling network is used for coupling each of the N different subsets of the input decoder outputs, which respectively contain precisely one output of each of the K input decoders, to the control connections of K instances of the controllable switches in one instance of the N drive paths which is associated with the subset in question, such that these switches turn on when those instances of the input decoder outputs which are coupled to them have been activated. Finally, a combinational logic device is provided which permits the drive paths to be connected fully only during the appearance of the turn-on signal. According to the invention, the combinational logic device is a device which is connected to all the outputs of one of the input decoders and responds to the turn-on signal in order to enable these outputs for coupling to the control connections of the switches associated with said outputs in the drive paths only during the appearance of the turn-on signal.
The object of the invention is thus to provide the means for logically combining the decoding with the turn-on signal not in the drive paths of the output decoder, as previously, but rather to move these means to the input decoder level. This is not difficult because it suffices to disable the outputs of only one of the K input decoders in order to prevent each of the N drive paths in the output decoder from being connected fully. Thus, at most, only as many individual logic combinations with the turn-on signal are required as there are outputs on the input decoder in question. This number is at most equal to 2m, if m is the number of bits in the associated segment of the input address. By contrast, in the prior art, where the logic combination with the turn-on signal was performed in the drive paths themselves, N=2M individual logic combinations were required, if M is the number of bits of the full address and all the bit combinations of the full address are used as the effective address (as is for the most part desirable and usual). By virtue of the invention, a large number of combinational logic elements are thus obviated, which is an advantage in itself.
The advantage relates not only to the number of combinational logic elements obviated, however, but also, in particular, to the locations at which they are obviated, namely the locations of the drive paths in the output decoder. By virtue of the invention, one switch fewer than in the prior art is required in each drive path. The space available for each drive path on a chip thus needs to be shared by fewer switches than previously. The space can therefore be better utilized for the channel length of the field effect transistors used as switches and/or for the distance between adjacent transistors. The latter point, in particular, improves the conditions for the success of obliquely directed halo implantation. The degree of miniaturization can therefore be increased beyond the level which has been possible to date.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a 1-out-of-N decoder circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.